ASIC DESIGN ENGINEER

Description

ASIC DESIGN ENGINEER #1653695 RESPONSIBILITIES: - Implementation and verification of high performance and low power clock distribution network - Perform schematic entry, spice simulation and optimization - Perform physical implementation using standard and/or semi-custom methodology - Perform physical verification including timing closure, robustness verification and LVS/DRC - Perform place and route and timing analysis - Interface with various stake holders (for example, logic design, logic verification, P&R, DFT and timing) to ensure that clock design meets all requirements - Support silicon debug and characterization MINIMUM REQUIREMENTS: - BS in Electrical Engineering with 1-4 years of experience in VLSI design - Strong understanding of deep submicron semiconductor technologies - Good team player - Hands-on experience in design and analysis for high performance and low power digital circuits - Hands-on experience in Synthesis (Design Compiler), STA tools (e.g. PrimeTime), place and route tools (ICC/Talus), RC extraction , EM/IR analysis and timing closure - Hands-on experience in transistor level design using SPICE - Strong programming skill in Perl and Tcl - Proficient in Verilog and formal verification - Knowledge of PLL, DLL, SRAM and IO design is preferred EOE