SR. SILICON FA ENGINEER

Description

SR. SILICON FA ENGINEER #1665616 nVidia Silicon Failure Analysis Lab is looking for FA analysts for our device analysis organization which supports product development/debug, manufacturing/yield, reliability and customer returns analysis of advanced flip chip devices manufactured in 28nm, and soon 20nm, 16nm and 14nm CMOS processes. We are looking for skilled, self directed, highly motivated individuals to join our team. The primary responsibilities of the applicant will be to perform fault isolation, DFT diagnostics and physical failure analysis using both conventional and advanced backside analytical instruments and techniques. The analyst will lead or support the development of product analysis capability, train / mentor less experienced analysts and participate in advanced tool related characterization and development projects. RESPONSIBILITIES: - Analyze BIST and ATE test data logs to identify and locate device failures for FA. - Create support programs and tests to further identify failure origins and causes to assist in determining the root cause of failures from the FIELD and from LOW YIELD analysis of production problems. - Support device analysis for detail design support in bring up and problem identification and characterization. - Create software to interface CAD Design and Simulation to the physical test and analysis to help determine weak areas and root cause solutions of device problems and failures. - Develop programs and support software for the new JTAG and BIST and current ATE test analysis, and integrate these into the FA Flow and improve time to failure identification to reduce cycle time for FA. - Knowledge of TEST (ATE test limitations, atpg generation, fault coverage, etc...) - Knowledge of CAD Support tools as used currently and future tools in order to integrate into the FA Flow. - Software languages as needed including PERL, TCL, C++, STYLE, and other CAD languages as they are added to the nVidia test flow from design, thru design for test, to atpg generation and into the ATE and post ATE analysis. MINIMUM REQUIREMENTS: - The position requires a technology related bachelor's degree plus related experience or equivalent combination of training and experience. - Applicants must have experience and demonstrated technical expertise in physical failure analysis based on parametric data, ATPG diagnostics and BIST isolation. - Functional knowledge of transistor device physics, advanced CMOS manufacturing processes, circuit analysis, advanced surface analysis analytical techniques and the UNIX operating system are also required. - Good written and verbal communication skills and ability to lead and organize projects are essential. EOE