SR VERIFICATION INFRASTRUCTURE ENGINEER

Description

SR VERIFICATION INFRASTRUCTURE ENGINEER #1674041 The NVIDIA GPU Verification team is looking for world class ASIC verification engineers to evolve and improve the core verification infrastructure for the development of discrete graphics and computing chips. The Verilog, SystemVerilog, UVM, C++, and Perl infrastructure encompasses several extensive applications that allow us to efficiently verify the world?s largest chips with a sophisticated distributed computing execution and triage environment. A key part of NVIDIA's strength is our unique and advanced development tools and environments that enable our incredible pace of new technology delivered to market. We are looking for verification and infrastructure experts for the next generation of our development and verification environments. You will join a fast-paced, agile team with high production quality standards. This role involves developing and improving testbench infrastructure, working closely with EDA vendors to develop and roll-out world-class development tools and methodologies, supporting very large scale distributed, cross-platform runs of mission critical proprietary applications and simulations, creating integrated development and debugging environments, creating and driving quality build and release processes, and driving the performance improvement of tools, simulations, and overall infrastructure. NVidia is continuously pushing the state of the art in chip development and needing the next generation of development environments to enable the next generation of chips. In this position, you will participate in the full tool development and release life cycle, working closely with other project members and the chip ASIC engineers to specify systems, create schedules, and manage ongoing feedback and enhancement releases. You will be using the best of your art in creating environments that are stable and easy to use by hundreds of engineers worldwide. You will learn and greatly improve the daily workflows of the world's top chip modelers and designers. MINIMUM REQUIREMENTS: - Strong object-oriented programming and design pattern knowledge: C++ preferred - Verification language skills: Verilog, SystemVerilog and UVM preferred - Excellent interpreted language skills highly desired - Perl preferred - Experience in ASIC design and development life cycle on Linux based platforms preferred - Experience with hardware verification, particularly in developing complex regression automations, testbenches, strongly desired - BS in Computer Science preferred - Excellent communication skills - Flexibility/adaptability for working in a dynamic environment with different frameworks and requirements EOE