SENIOR STATIC TIMING METHODOLOGY AND SUPPORT ENGINEER

Description

SENIOR STATIC TIMING METHODOLOGY AND SUPPORT ENGINEER #1557980 The ideal candidate for this role will have extensive project based STA experience as well as experience in STA flow development. You will be supporting the day to day STA activities of physical design teams across the company. This will require you to gain an understanding our STA flows and contribute to their improvement by developing and/or enhancing their current functionality. MINIMUM REQUIREMENTS: - BS in EE, CE, CS or equivalent - Expertise in Primetime, or other industry standard STA tools, and Verilog - Experience in large design STA and timing closure - Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects - Strong knowledge of physical design from synthesis through tapeout - Great Object oriented programmer in Perl, C++. Java or Python, with a track record in development of well structured, supportable, and testable code - Ability and drive to understand the motivation for tools, where they fit into the flow, how to prioritize features and to decide the best way to implement. - Prior methodology development experience EOE