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NVIDIA

Santa Clara, California - United States
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SENIOR MIXED SIGNAL DESIGN ENGINEER

Description

SENIOR MIXED SIGNAL DESIGN ENGINEER Architecture and design of CMOS high-speed chip interfaces (HDMI, LVDS, DVI, PCIE, USB) and other complex analog functions. Strong hands-on experience in the lab with silicon evaluation, debugging, characterization, and bring up. RESPONSIBILITIES: - Design and implementation of high speed interfaces and analog circuits. - Circuit Design Projects may include working with high speed interfaces, high speed frequency synthesis PLLs. - Design, simulate, and verify analog and complex mixed-signal CMOS circuits. - Supervise closely IC Circuit / Mask designers, provide floor plan and layout guidelines. - Support technology transfer to product development teams. - Support debug and characterization of design. - If you have a strong ability to learn and explore new technologies and are able to demonstrate good analysis and problem solving skills, this is the ideal position for you. MINIMUM REQUIREMENTS: - MS or Phd in Electrical Engineering. - 3+ years deep sub-micron process design experience in CMOS Analog / Mixed Signal Circuit Design. - Demonstrated experience in designing and mentoring designers in biasing circuits, band gap references, regulators, op-amps, and PLL blocks. - Requires strong fundamental understanding of transistor level analog design concepts and deep submicron processes / technology. - Interpolators, spread spectrum, high speed PLL / DLLs and timing related circuitry as well as clock path and buffer optimization for optimum area efficiency and high speed operation. - Experience in one or more of these high speed interfaces (serial link, GDDR5), digital links such as HDMI, LVDS, DVI, PCIE, USB. - You will also need a good understanding of Cadence's custom IC design environment, analog circuit simulation (HSpice, HspireRF), Finesim, XA, verilog. Programming language skills (Perl) as well as digital design skills are a plus. - Candidate must demonstrate a substantial background in pertinent project work and demonstrate deep/intimate understanding and knowledge of high-speed data communication and relevant circuit concepts. EOE

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