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NVIDIA

Santa Clara, California - United States
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DFT/YIELD ANALYSIS ENGINEER

Description

DFT / YIELD ANALYSIS ENGINEER #1650906 We are currently seeking a candidate to be responsible for improving defect isolation and yield analysis of test vehicles to accelerate yield learning and process characterization. RESPONSIBILITIES: - Work with DFT and external vendors to improve defect isolation and characterization - Drive cutting edge new techniques in the yield analysis field to improve understanding of yield loss - Implement and maintain a variety of analysis scripts used to understand test vehicles failures - Interact with internal and external cross-functional groups to optimize bring-up of future process nodes and rollout to production MINIMUM REQUIREMENTS: - Strong fundamental knowledge of DFT techniques - Strong knowledge of diagnosis and failure isolation - Good background in analysis techniques and tools including JMP/R - Good programming knowledge including one or more of the following; C, C++, TCL or Perl. - Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models. - Knowledge in memory defect models and test algorithms a plus - Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing. - Experience with Synopsys Tetramax and Yield Explorer a plus - Detail oriented with strong organizational, problem solving and communication skills. - Master's, Computer Engineering and/or Electrical Engineering - Prefer 2 years experience or more EOE

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