SENIOR ASIC (CLOCKS) DESIGN ENGINEER

Description

SENIOR ASIC (CLOCKS) DESIGN ENGINEER #1622716 The NVIDIA Clocks group is looking for a top ASIC engineer with extensive experience in high-speed logic design and verification. In this position, you will have the opportunity to be responsible for the architecture, design, verification and physical design of complex clocking networks in large GPUs and SOCs. The complexity of Nvidia's clocking structures has grown substantially by supporting multiple high frequency clock domains as well as variety of DFT, power, noise, circuit, physical design features and constraints. In this position, you will have the opportunity to look ahead to future technologies and make tradeoffs at different levels of design abstraction to create novel and efficient clocking structures. MINIMUM REQUIREMENTS: - BS or MS (preferred) in EE, with a minimum of 4 years of relevant industry work experience - Experience in RTL design (Verilog), verification and synthesis - Strong coding skills in Perl or other industry-standard scripting languages - Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects - Prior experience in implementing on-chip clocking networks is a plus - Excellent communication skills and ability to interface with many groups and build consensus EOE