SR. MEMORY SYSTEM ARCHITECT

Description

SR. MEMORY SYSTEM ARCHITECT #1643132 NVIDIA is building the world's fastest highly-parallel processing systems, period. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In addition we are adding a lot of virtualization and programming model capabilities. RESPONSIBILITIES: - Drive new memory system architectures from DRAM up. - Explore architecture trade-offs in system performance, area, and power consumption. - Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). - Add virtualization capabilities to the system. - Develop performance simulators, models and test suites. - Develop functional simulators, models and test suites. MINIMUM REQUIREMENTS: - MS or PhD in a relevant area. - A demonstrated history of technical leadership. - 5+ years of architecture research and/or development of memory or highly interconnected system architectures. - 5+ years of research and development experience in performance analysis, tools, or simulators. - 5+ years of C/C++ development. - Knowledge of high performance memory system or interconnect architectures, experience with various virtualization techniques, including performance modeling and functional modeling and analysis. - Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results. - Ideal candidates will have experience in High-Performance Computing (HPC), Virtualization, Memory Hierarchies, Interconnect Architectures, and System Architecture. EOE